A. Field of the Invention
The present invention relates to a reverse-conducting insulated gate bipolar transistor (hereinafter also abbreviated to an RC-IGBT) that is provided with an insulated gate bipolar transistor (hereinafter also abbreviated to an IGBT) and a diode that is anti-parallel-connected to the IGBT, both disposed on one and the same semiconductor substrate.
B. Description of the Related Art
Performance improvement in power semiconductor devices is in progress in insulated gate bipolar transistors (IGBTs) and free-wheeling diodes (FWDs) for withstand voltage class of 600 V, 1,200 V, and 1,700 V. Those power semiconductor devices are used in high speed, high efficiency and power saving power conversion equipment including converters and inverters, and are indispensable for controlling rotating motors and servo motors. The power control apparatuses confront growing requests of the market for low losses (power saving), high speed, high efficiency, and environment-friendly characteristics. In order to address to these requests, the procedure of manufacturing an IGBT comprises a step of grinding the wafer from the rear surface side, which is an opposite side of the MOS gate side, to be as thin as possible while maintaining the necessary performance. The grinding step is carried out at a stage as late as possible in the wafer processing that has started with a conventionally employed thick wafer in consideration of preventing the wafer from cracking in the wafer processing. Moreover, a method of manufacturing a semiconductor device which provides low electric losses (low switching loss and low ON-state voltage drops) at a low cost has been developed, in which ion implantation of impurity elements from the ground rear surface side and a following activation treatment are conducted at an impurity concentration carefully selected in the design process. A main stream nowadays in development and manufacture of a power semiconductor device in particular is a manufacturing method for a semiconductor device with a thin semiconductor substrate providing a low loss performance at a low cost. For a low loss IGBT in particular, a step is essential for introducing and forming a so-called field stop region, a layer to stop expansion of a depletion layer before reaching a p+ collector region, in the ground rear surface side. Further, for minimizing a chip size containing the IGBT and accompanying parts, reverse conducting IGBTs (RC-IGBTs) are being developed, the RC-IGBT incorporating an IGBT and an anti-parallel-connected FWD together in one and the same semiconductor substrate.
Japanese Unexamined Patent Application Publication No. 2004-363328 (FIG. 1 in particular) discloses a type of RC-IGBT with a structure in which a semiconductor chip is divided into two regions on the chip surface, and a principal active region of an IGBT region and a principal active region of a FWD region are arranged side by side in the two divided regions. Japanese Unexamined Patent Application Publication No. 2005-101514 (FIG. 1 in particular) discloses an RC-IGBT of a collector-shorted type in which the front surface region comprises solely a MOS gate region having a surface pattern similar to an ordinary IGBT, and the rear surface region comprises both an n+ type cathode region for a FWD region and a p+ type collector region for an IGBT region arranged side by side. In the arrangement for anti-parallel connection of the IGBT and the FWD, chip area is saved by sharing an edge termination structure at the outer periphery of the chip. This structure provides a relatively large area reduction effect of about 20% when employed in devices for a small current ratings (not larger than 20 A) since a proportion of an area occupied by the edge termination structure is relatively large.
Japanese Patent No. 4097416 (FIG. 1 in particular) and Japanese Unexamined Patent Application Publication No. 2008-042073 (FIG. 2 in particular) also disclose RC-IGBTs of a so-called collector-shorted type as well as Japanese Unexamined Patent Application Publication No. 2005-101514. In a collector-shorted type IGBT having an n+ cathode region and a p+ collector region together in the collector region side in the rear surface side, as compared with an IGBT having solely a p+ collector region, electrons injected from the MOS gate structure in the gate ON state drain easily towards the n+ cathode region of the FWD region and barely accumulate around the pn junction surface. As a result, an electric potential of the p+ collector region hardly exceeds the built-in voltage. Consequently, in order to inject positive holes from the p+ collector region in an IGBT of a collector-shorted type and perform conductivity modulation in a drift layer of the IGBT, some means needs to be devised in which a voltage drop due to the electron current running along the junction surface exceeds the built-in voltage (about 0.8 V) at the pn junction in the process of passing-through of the electrons in the vicinity of the p+ collector region towards the n+ cathode region. This phenomenon is called a latching up phenomenon. Further, when a high impurity concentration n+ region such as a field stop region is formed, the electrons injected from the MOS gate runs towards the n+ cathode region via this field stop region. Consequently, the voltage drop becomes extremely small especially around the junction surface, resulting in little possibility of latching up. (The voltage drop is a wording when the electron flow is considered as current of electricity, and the direction of flow of the electrons is opposite to the direction of flow of electric current.) Since a large magnitude of electron current is necessary to attain a voltage drop value around the junction surface required by the latching up, a “snap-back” occurs in the I-V waveform in the ON state causing a difficult condition for turning the IGBT region ON (or a difficult condition for latching up). Japanese Unexamined Patent Application Publication No. 2007-184486 (FIG. 4 in particular) discloses a method for easy latching up in which trenches are formed from a surface of a p+ collector region in the rear surface side to a relatively deep position in the n-type layer to physically shield the n+ cathode region partly, thereby increasing the electric resistance along direction of the junction surface, thus facilitating the latching up.
In a conventional RC-IGBT and a collector-shorted type IGBT, the latching up phenomenon described above is indispensable for achieving the conductivity modulation in a drift layer. Nevertheless, the latching up is not easy to achieve and a snap-back phenomenon is apt to occur caused by the existence of an n+ cathode region in a p+ collector region side, in comparison with an ordinary IGBT that is not a reverse-conducting type or a collector-shorted type. On the other hand, in order to achieve low switching loss and small current conduction loss, a field stop region with a high impurity concentration (hereinafter referred to as an n+ FS region) needs to be provided at the p+ collector region side in the n drift layer. However, the n+ FS region has a high impurity concentration and a low resistivity. Consequently, the n+ FS region exhibits a small voltage drop function that would be obtained by the electron injection, and becomes a factor that inhibits the latching up. Thus, an RC-IGBT for power conversion apparatuses has two inherent factors that inhibit latching up.
In the structure disclosed in Japanese Unexamined Patent Application Publication No. 2004-363328, the principal active region is divided into two portions: one for the FWD and the other for the IGBT. In this structure, a length (a width) of the p+ collector region in the rear surface side of the IGBT region in the direction along the rear surface must be at least 100 μm in order to facilitate attaining a voltage drop value larger than the built-in voltage accompanied by electron current around the junction surface. In the case of provision of a low resistivity n+ FS region in particular, this width must be a still larger value of 200 μm to 300 μm. On the other hand, a rate of area reduction obtained by integrating an IGBT and an FWD monolithically into one chip is yet a small value not larger than 20% in a device of small current rating of 20 A class. In addition, in consideration of the cost increase due to the increased number of steps and an additional material cost in the actual chip cost, a cost reduction rate obtained by the monolithic integration drops to a value of at most 10%. Consequently, in order to ensure a 30% reduction in chip cost, the area of a chip needs to be reduced by at least 40%. However, in a method to integrate an IGBT region and an FWD region monolithically into one chip, an integrated structure obtained by simply dividing the major active region of a semiconductor substrate into two regions as disclosed in Japanese Unexamined Patent Application Publication No. 2004-363328 is absolutely impossible to provide a cost reduction effect of 30%. Moreover, in the RC-IGBT structure provided with an n+ FS region as described previously, in which a width of not smaller than 200 μm is ensured in the IGBT region itself, the FWD region needs an area corresponding to a width of about 100 μm, thus requiring an active region with a length (a width) of at least 300 μm. In the structure disclosed in Japanese Unexamined Patent Application Publication No. 2007-184486, in which a p+ collector region (in the IGBT region) and an n+ cathode region (in the FWD region) are separated from each other by a deep trench formed from the rear surface, an overall length of the IGBT region can be surely reduced. However, in a case of the length of the IGBT region shorter than 100 μm, the electrons injected from the MOS gate structure goes towards the FWD region in the middle of the n drift layer deeper than the bottom of the trench according to the electrostatic potential distribution, causing the latching up to occur hardly. Therefore, the RC-IGBT cannot benefit from the integration of the IGBT region and the FWD region into a single chip by means of the method disclosed in Japanese Unexamined Patent Application Publication No. 2007-184486, and the chip cost cannot be reduced yet.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.